Generally, a semiconductor memory device has a back (substrate) bias voltage (Vbb) generator for applying the back bias voltage to the substrate of the semiconductor memory device. Such a technology is disclosed in U.S. Pat. No. 4,775,959 which is incorporated herein by reference.
In U.S. Pat. No., 4,775,959, a back bias voltage (hereinafter referred to as "Vbb") generator circuit in a semiconductor memory device uses a/RAS1 signal, which is delayed by a timing control circuit TC from a row address strobe signal /RAS, and is activated by an input signal of a voltage level detection circuit (hereinafter referred to as the "VLD" section) and the /RAS1 signal.
Timing control circuit TC, as shown in FIG. 1, receives the row address strobe signal /RAS, the column address strobe signal /CAS, and a write enable signal /WE that are supplied from external terminals, and generates various timing signals necessary for the memory operation, e.g., /RAS1.
Herein, the VLD section senses whether the base back bias voltage level exceeds a predetermined voltage level.
As illustrated in FIG. 2, the Vbb generator circuit includes first Vbb generator Vbb-G1 and second Vbb generator Vbb-G2. The VLD section has three NMOS diodes Q12-Q14 and two PMOS transistors Q10 and Q11 which are serially connected between Vcc and Vbb. A signal on node "A" passes to an invertor constituted with pMOSFET Q15 and nMOSFET Q16 and invertors IVO and IV1 to an one input of NAND gate G1. The other input of the NAND gate G1 is connected to a terminal receiving the /RAS1 signal.
First Vbb generator Vbb-G1 of Vbb generator circuit Vbb-G comprises second oscillator OSC2, a buffer portion having invertors IV4 and IV5 for buffering a signal from second oscillator OSC2, pumping capacitor C2, and a rectifying portion having diodes Q20 and Q21, which are connected to pumping capacitor C2 and between ground GND and substrate Vbb.
The second Vbb generator Vbb-G2 comprises first oscillator OSC1 including three NAND Gates G2-G4, a buffer portion which comprises two invertors IV2 and IV3, which are series-connected to the output stage of first oscillator OSC1, and a rectifying portion with NMOS transistors Q18 and Q19 series connected through pumping capacitor Cl from the output stage of the buffer portion.
Herein, capacitor C1 as the pumping capacitor of second Vbb generator Vbb-G2 has a big capacitance and capacitor C2 of the first Vbb generator Vbb-G1 has a smaller capacitance than capacitor Cl.
FIG. 3 is a timing chart for explanation of an operation of Vbb generator circuit Vbb-G of FIG. 2.
With respect to the conventional semiconductor memory device as explained above, an operation of Vbb generator Vbb-G1 is explained. If power source Vcc is applied to Vbb generator Vbb-G1, an oscillation signal with a predetermined pulse rate subsequently is output from second oscillator OSC2. If the oscillating signal of second oscillator OSC2 is high, diode Q20 is turned-on so that one electrode of capacitor C2 as the pumping capacitor is connected to the ground and charges the ground level. If the oscillating signal of second oscillator OSC2 is low, diode Q20 is turned-off and diode Q21 is turned-on so that one electrode of capacitor C2 becomes a more negative voltage level than ground level. Thus, diode Q21 is turned-on and is connected electrically to Vbb, which is lowered in the negative direction. Such operation continues while the electric power source is applied thereto.
The driving power of first Vbb generator Vbb-G1 is weak to the extent that it compensates as much as the leakage current of the transistors in the chip when operating in a stand-by mode.
The main back bias voltage generator, second Vbb generator Vbb-G2, combined with the VLD section, has a relatively large driving capacity for generating a negative voltage.
If Vcc is applied to these portions, as PMOS transistor Q10 is turned-on and node "A" is "high", PMOS transistor Q15 is off and node "B" is "low" ; as the "low" signal is reversed by invertor IVO, node "C" is "high" ; and as it is again reversed in invertor IV1, node "D" as the output stage is "low", thereby being applied to one input of NAND Gate G1.
If the /RAS1 signal, which is delayed a little from the /RAS signal, is applied as "low", NAND gate G1 output node "E" is "high", so that first oscillator OSC1 operates and its oscillating signal is applied to capacitor C1 through the buffer portion, and thereby the negative voltage is applied to the substrate through node-Vbb by the operation of diodes Q18 and Q19 of the rectifying portion by pumping operation of capacitor Cl.
When the negative voltage is continuously applied, and thus the voltage level of Vbb goes below -3Vth as shown in FIG. 3, diodes Q12-Q14 of the VLD section are in a forward direction and turned-on, thereby PMOS transistor Q11 is on and therefore node "A" is "low", node "B" is "high", node "C" is "low" and node "D" is "high".
In this state, operation of first oscillator OSC1 is controlled by the /RAS1 signal. If the /RAS1 signal is "high", i.e., in a stand-by mode, then first oscillator OSC1 stops its operation, thereby stopping the pumping operation of capacitor Cl. If the /RAS1 signal is "low", i.e., in an active state, then first oscillator OSC1 continues negative pumping.
While the chip is in a stand-by mode, most transistors are off and the leakage current is relatively small due to operation of equalizer or pre-charge transistors. Therefore, in this status, consumption of electric power required for stand-by mode can be reduced by operating only first Vbb generator Vbb-G1, which has a small driving capacity.
Otherwise, if the chip is active or the voltage level of the Vbb does not reach below -3Vth, the chip is active by operation of second Vbb generator Vbb-G2 having a large driving capacity, and many transistors are operated, thereby preventing a rise of the Vbb voltage caused by a relatively large amount of leakage current, so that it is possible to realize safe operation of the chip.
In such kinds of conventional semiconductor memory devices, the Vbb generator should be increased according to an increase of the memory capacity. However, for the array block located farthest from the Vbb generator, the Vbb voltage of the farthest array block rises due to the delay in transmitting the Vbb voltage from the Vbb generator. In this regard, there occurs a problem of degrading the reliability of the semiconductor memory device, since operation errors of the array block might occur.